LBME=Val_0x0, TPSS=Val_0x0, TSSS=Val_0x0, RACTIVE=Val_0x0, TACTIVE=Val_0x0, LBMI=Val_0x0, BUSOFF=Val_0x0, RESET=Val_0x0
Configuration and Status Register
| BUSOFF | Bus Off (Bus Status Bit, refer to Section Error Handling). Writing a 0x1 to this bit will reset the CANFD_TECNT and CANFD_RECNT registers. This should be done only for debugging. For more details, refer Section Error Counter Reset. 0 (Val_0x0): The controller status is bus on 1 (Val_0x1): The controller status is bus off |
| TACTIVE | Transmission ACTIVE (Transmit Status Bit). 0 (Val_0x0): No transmit activity 1 (Val_0x1): The controller is currently transmitting a frame |
| RACTIVE | Reception ACTIVE (Receive Status Bit). 0 (Val_0x0): No receive activity 1 (Val_0x1): The controller is currently receiving a frame |
| TSSS | Transmission Secondary Single Shot Mode for STB (refer to Section Single Shot Transmission (SST)). 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |
| TPSS | Transmission Primary Single Shot Mode for PTB (refer to Section Single Shot Transmission (SST)). 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |
| LBMI | Loop Back Mode, Internal (refer to Section Loop Back Mode (LBMI and LBME)). Note that this bit should not be enabled while a transmission is active. 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |
| LBME | Loop Back Mode, External (refer to Section Loop Back Mode (LBMI and LBME)). Note that this bit should not be enabled while a transmission is active. 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |
| RESET | RESET Request Bit. Some registers can only be modified if the RESET bit is set to 0x1. This bit forces several components to a reset state. A detailed definition is given in Section Software Reset. It is automatically set if the node enters bus off state (refer to Section Error Handling). Note that a CAN node will participate in CAN communication after the RESET bit is switched to 0x0 after 11 CAN bit times. This delay is required by the CAN standard (bus idle time). If the RESET bit is set to 0x1 and immediately set to 0x0, then it takes some time until it can be read as 0x0 and becomes inactive. The reason is clock domain crossing from host to CAN clock domain. The RESET bit is held active as long as needed depending on the relation between host and CAN clock. 0 (Val_0x0): No local reset of the CAN controller 1 (Val_0x1): The host controller performs a local reset of the CAN controller |